1. Field of the Invention
The present invention relates to a compound semiconductor switch circuit device. In particular, the present invention relates to a compound semiconductor switch circuit device in which isolation is improved.
2. Description of the Related Art
In mobile communication instruments such as cellular phones, microwaves in the GHz band are often used. In many cases, switch elements for switching among such high-frequency signals are used in antenna switch circuits and transmit-receive switch circuits. Since such switch elements deal with high frequencies, field-effect transistors (hereinafter referred to as “FETs”) constructed using gallium arsenide (GaAs) are often used as the switch elements. Along with this, monolithic microwave integrated circuits (MMICs) are being developed into which the switch circuits themselves are integrated.
Further, as illustrated in FIG. 15, a technology is known in which protecting elements 200 having n+/i/n+ structures are connected between two terminals of an element to be protected, in order to greatly improve electrostatic breakdown voltage in a compound semiconductor device.
FIG. 15 illustrates a compound semiconductor switch circuit device called a singlepole doublethrow (SPDT) switch constructed using GaAs FETs.
The sources (or drains) of FET1 as a first FET and FET2 as a second FET are connected to a common input terminal IN. The gates of FET1 and FET2 are connected to first and second control terminals Ctl1 and Ctl2 through control resistors R1 and R2, respectively. The drains (or sources) of the FETs are connected to first and second output terminals OUT1 and OUT2, respectively. Control signals applied to the first and second control terminals Ctl1 and Ctl2 are complementary signals. Of the FETs, one to which an H-level signal is applied is turned on, whereby a high-frequency analog signal inputted to the common input terminal IN is transmitted to either of the output terminals.
Pads I, O1, O2, C1, and C2 which respectively serve as the common input terminal IN, the first and second output terminals OUT1 and OUT2, and the first and second control terminals Ctl1 and Ctl2 are provided around FET1 and FET2 in a peripheral portion of a substrate.
Source and drain electrodes 315 and 316 of FET1 are placed in a state in which comb-teeth-like portions are engaged. The gate electrode 317 thereof is placed between the source and drain electrodes 315 and 316.
A peripheral impurity region 350 for improving isolation is provided around each pad 330. Further, the control resistors R1 and R2, which are impurity regions, are placed near the common input terminal pad I and the first and second output terminal pads O1 and O2. Thus, protecting elements 200 having n+/i/n+ structures are connected between the input terminal IN and the first control terminal Ctl1 (or second control terminal Ctl2) and between the first output terminal OUT1 (or second output terminal OUT2) and the first control terminal Ctl1 (or second control terminal Ctl2), and static electricity is discharged. This technology is described for instance in Japanese Patent Application Publication No. 2004-103786.
FIG. 16 illustrates a circuit diagram of FIG. 15, and FIGS. 17A to 17C illustrate schematic diagrams of the switch MMIC of FIG. 15 in operation.
As illustrated in FIG. 15, the control resistors R1 and R2, which respectively connect the first and second control terminal pads C1 and C2 with FET1 and FET2, are extended in a chip and placed near the input terminal pad I and the first and second output terminal pads O1 and O2.
It is effective that electrostatic energy applied between the common input terminal IN and the first control terminal Ctl1 (or second control terminal Ctl2) is discharged immediately near the pads which serve as these terminals. Accordingly, protecting elements 200 are preferably connected in the vicinities of the pads.
The peripheral impurity regions 350 for improving isolation are respectively placed around the pads. Further, the first and second control terminal pads C1 and C2 are respectively connected to the gate electrodes of FET1 and FET2 using connecting paths, which are impurity ion-implanted regions. Each of these connecting paths is an impurity region and is the resistor (control resistor) R1 (or R2) having a predetermined resistance value. The connecting paths prevent high-frequency signals from leaking from the gate electrodes to the control terminals which are at GND potential for high frequencies.
Accordingly, the control resistor R1 (or R2) is placed along and near the common input terminal pad I to be spaced therefrom by a distance of 4 μm. The control resistor R1 (or R2) includes a resistor R11 (or R21) of 2 kΩ and a resistor R12 (or R22) of 4 kΩ and the like. Thus, a protecting element 200b including the control resistor R1 (or R2), the peripheral impurity region 350, and an insulating region (GaAs substrate) therebetween is connected between the common input terminal IN and the first control terminal Ctl1 (or second control terminal Ctl2). Accordingly, the above-described pattern can greatly improve electrostatic breakdown voltage.
Further, the control resistor R1 (or R2) is placed along and near the first output terminal pad O1 (or the second output terminal pad O2) to be spaced therefrom by a distance of 4 μm.
Thus, a protecting element 200a including the control resistor R1 (or R2), the peripheral impurity region 350, and an insulating region (GaAs substrate) therebetween is connected between the first output terminal OUT1 (or second output terminal OUT2) and, the first control terminal Ctl1 (or second control terminal Ctl2). Accordingly, the above-described pattern can greatly improve the minimum value of electrostatic breakdown voltage.
However, in the case where the control resistor R1 (or R2) is placed near the common input terminal pad I and the first output terminal pad O1 (or second output terminal pad O2), there arises the problem that isolation is deteriorated.
FIGS. 17A to 17C are diagrams each illustrating an overview of a switch MMIC in operation. The switch MMIC is similar to that of FIG. 15. However, FIGS. 17A and 17B are diagrams for the case where the protecting elements 200 are not connected, i.e., the case where the control resistor R1 is placed without being close to each pad; and FIG. 17C is a diagram for the case where the protecting elements 200 are connected as in FIG. 15. It should be noted that FET1 and FET2 are symmetrically placed and have similar structures. Accordingly, the FET1 side will be described below.
FIG. 17A is a schematic cross-sectional view of FET1 when an electrical path between the common input terminal IN and the first output terminal OUT1 is off, i.e., when the FET1 side is off. Further, FIG. 17A corresponds to a cross-sectional view taken along line p-p of FIG. 15. However, FIG. 17A is a schematic diagram for explaining the state of operation, and therefore does not completely coincide with the structure of the FET of FIG. 15.
In the substrate surface in the region of the FET illustrated in FIG. 15, a channel layer 312 is provided which is an impurity-implanted region. On the surface of the channel layer 312, for example, a source electrode 315 which is on the common input terminal IN side and a drain electrode 316 which is on the first output terminal OUT1 side are placed, and a gate electrode 317 is provided therebetween to form a Schottky junction with part of the channel layer 312.
Further, when FET1 is off, a depletion layer 500 spreads in the channel layer 312 under the gate electrode 317 as illustrated in FIG. 17A and reaches a bottom portion of the channel layer 312 to pinch off the channel. Thus, the channel layer 312 is cut off. That is, in the case where the protecting elements 200 are not connected, FET1 is the only path through which a high-frequency analog signal inputted from the source electrode 315 on the common input terminal IN side is transmitted to the drain electrode 316 on the first output terminal OUT1 side.
In the switch MMIC, signals need to be prevented from leaking between the terminals of an FET (FET1 here) in an off state. To do so, it is desirable that the channel layer 312 is sufficiently cut off with the depletion layer 500 as illustrated in FIG. 17A to improve isolation.
FIG. 17B is an equivalent circuit diagram of FIG. 17A. The depletion layer 500 becomes a capacitive component, and FET1 in off state is in a state in which a capacitance between the gate terminal G and the source terminal S and that between the gate terminal G and the drain terminal D are connected in series. Further, the value of isolation is determined by the combined capacitance of the two capacitances.
FIG. 17C is a conceptual diagram of the control resistor R1 in the chip pattern diagram of FIG. 15.
In the chip pattern diagram of FIG. 15, the protecting elements 200b and 200a are formed by the control resistor R1 passing near the common input terminal pad I and the first output terminal pad O1, respectively.
Further, the resistor R11 of 2 kΩ is connected between the protecting element 200a and the gate terminal G of FET1, and the resistor R12 of 4 kΩ is connected between the protecting elements 200a and 200b. That is, each of these has a low resistance value of not more than 5 kΩ.
Thus, a path p1 for a high-frequency signal occurs between the drain terminal D and the gate terminal G of FET1 by the resistor R11 of 2 kΩ between the protecting element 200a on the first output terminal pad O1 side and the gate terminal G (gate electrode 317) and the parasitic capacitance of the protecting element 200a. Since a high-frequency signal leaks along this path p1, there is the problem that isolation is deteriorated.
Moreover, the resistance value of R12 between the protecting element 200a on the first output terminal pad O1 side and the protecting element 200b on the common input terminal pad I side is also 4 kΩ, which is not more than 5 kΩ. Accordingly, a path p2 for a high-frequency signal occurs between the drain terminal D and the source terminal S of FET1 (between the first output terminal pad O1 and the common input terminal pad I) by the resistor R12 of 4 kΩ and the parasitic capacitances of the protecting elements 200a and 200b. Since a high-frequency signal leaks along this path p2, there is the problem that isolation is further deteriorated.